Analysis and Design of Low Power Scan D Flip Flop Based on Positive Edge Trigger
نویسندگان
چکیده
Power dissipation of IC during test mode is greater than the IC’s normal mode of functioning. Power consumption in scan based testing is high due to the toggling of the combinational logic during the scan shift.In digital systems power reduction is the most critical issue. A FLIP FLOP is a one bit storage device used for storage device used for storage purpose. Mostly used d-flip flop in digital circuits has been modified in this paper introducing SCAN D FLIP FLOP. This reduces the power by avoiding unnecessary states. SCAN D Flip flop has high speed compare to normal D Flip flop. The Scan D flip flop is introducing in 130nm technology used on the positive edge trigger clock pulse.
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